1. Field of the Invention
The present invention relates to integrated circuit manufacturing, and more particularly to insulated-gate field-effect transistors.
2. Description of Related Art
An insulated-gate field-effect transistor (IGFET), such as a metal-oxide semiconductor field-effect transistor (MOSFET), uses a gate to control an underlying surface channel joining a source and a drain. The channel, source and drain are located in a semiconductor substrate, with the source and drain being doped oppositely to the substrate. The gate is separated from the semiconductor substrate by a thin insulating layer such as a gate oxide. The operation of the IGFET involves application of an input voltage to the gate, which sets up a transverse electric field in order to modulate the longitudinal conductance of the channel.
In typical IGFET processing, the source and drain are formed by introducing dopants of second conductivity type (P or N) into a semiconductor substrate of first conductivity type (N or P) using a patterned gate as a mask. This self-aligning procedure tends to improve packing density and reduce parasitic overlap capacitances between the gate and the source and drain.
Polysilicon (also called polycrystalline silicon, poly-Si or poly) thin films have many important uses in IGFET technology. One of the key innovations is the use of heavily doped polysilicon in place of aluminum as the gate. Since polysilicon has the same high melting point as a silicon substrate, typically a blanket polysilicon layer is deposited prior to source and drain formation, the polysilicon is anisotropically etched to provide a gate which provides a mask during formation of the source and drain by ion implantation, and then the implanted dopant is activated using a high-temperature anneal that would otherwise melt the aluminum.
As IGFET dimensions are reduced and the supply voltage remains constant (e.g., 3 V), the electric field in the channel near the drain tends to increase. If the electric field becomes strong enough, it can give rise to so-called hot-carrier effects. For instance, hot electrons can overcome the potential energy barrier between the substrate and the gate insulator thereby causing hot carriers to become injected into the gate insulator. Trapped charge in the gate insulator due to injected hot carriers accumulates over time and can lead to a permanent change in the threshold voltage of the device.
A number of techniques have been utilized to reduce hot carrier effects. One such technique is a lightly doped drain (LDD). The LDD reduces hot carrier effects by reducing the maximum lateral electric field. The drain is typically formed by two ion implants. A light implant is self-aligned to the gate, and a heavy implant is self-aligned to spacers adjacent to sidewalls of the gate. The spacers are typically oxides or nitrides. The purpose of the lighter first dose is to form a lightly doped region of the drain (or LDD) at the edge near the channel. The second heavier dose forms a low resistivity region of the drain, which is subsequently merged with the lightly doped region. Since the heavily doped region is farther away from the channel than a conventional drain structure, the depth of the heavily doped region can be made somewhat greater without adversely affecting the device characteristics.
Complementary metal-oxide semiconductor (CMOS) circuits include N-channel (NMOS) devices and P-channel (PMOS) devices. Conventional processes typically use N-well masks and P-well masks early in the processing sequence to define the NMOS and PMOS regions. Conventional process also typically include a single masking step for forming the gates over the NMOS and PMOS regions, separate masking steps for implanting lightly doped N-type source/drain regions into the NMOS region and lightly doped P-type source/drain regions in the PMOS region, formation of spacers adjacent to the gates, and then separate masking steps for implanting heavily doped N-type source/drain regions into the NMOS region and heavily doped P-type source/drain regions into the PMOS region.
A procedure has been reported that requires only one masking step for creating source and drain regions in the NMOS and PMOS regions. With this procedure, after the gates are formed, heavily doped P-type source/drain regions are nonselectively implanted into the NMOS and PMOS regions, a mask is formed that covers the PMOS region and exposes the NMOS region, and heavily doped N-type source/drain regions are implanted into the NMOS region which counterdope the P-type source/drain regions in the NMOS region. See SILICON PROCESSING FOR THE VLSI ERA, Volume 2: Process Integration, by S. Wolf, published by Lattice Press, Sunset Beach, Calif., p. 436 (1990). The procedure can be extended to fabricating NMOS and PMOS devices with lightly and heavily doped source and drain regions using three masking steps instead of four. In particular, lightly doped P-type source/drain regions are implanted into the NMOS and PMOS regions, a first mask covers the PMOS region and exposes the NMOS region, lightly doped N-type source/drain regions are implanted into the NMOS region which counterdope the lightly doped P-type source/drain regions in the NMOS region, spacers are formed adjacent to the gates, and heavily doped source/drain regions are implanted into the NMOS and PMOS regions using separate masking steps.
A drawback to this procedure, however, is that the gate for the NMOS device is doped with both N-type and P-type dopants. The dual-doped gate may lead to difficulties, for instance, in obtaining the desired threshold voltage, or in properly forming a gate salicide contact.
Accordingly, a need exists for an improved method of making a N-channel and P-channel devices with reduced masking steps and without subjecting either gate to both N-type and P-type dopants.